project new E:/Project/DMA/pcores/nids_v1_00_a/devl/projnav/nids.xise;
project set family virtex6;
project set device xc6vlx240t;
project set package ff1156;
project set speed -1;
project set top_level_module_type HDL;
project set synthesis_tool "XST (VHDL/Verilog)";
lib_vhdl new nids_v1_00_a;
xfile add E:/Project/DMA//pcores/nids_v1_00_a/hdl/verilog/nids.v;
project close;
